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reasonable VLSI systems in general are heterogeneous, i.e. they consist of both hardware and software components. Parts of the system, which are not subject to tight computation-speed constraints, are better realized by software running on programmable processors, while other parts might require fast, dedicated hardware. It is advantageous to implement as much of a system as possible in software, because software is cheaper and more flexible. This trend creates a need for software compilers as a part of electronic computer-aided design systems. Such compilers need to be linked to hardware design tools and must provide a certain flexibility. The consumer market needs for the processor architectures tailored towards certain application domains, usually in the sense of higher level of optimization. In contrast to the programmation of general-purpose computers, where the user repeatedly programmes and configures his PC so as to solve a variety of problems, such special-purpose processors are designed only once to serve a single, particular application. They interact with larger, often non-electronic environments and are therefore called embedded systems. In a heterogeneous embedded system, its software components are stored in the program ROM of the system and executed on programmable embedded processor(s). Obviously, the software must be prepared in the internal language of the processor. But, when designing an embedded systems, the hardware and software components are both designed starting from a purely functional description of the system. The first step of the design is the hardware-software partitioning, i. e. the decision whether to assign different components of the system to either hardware or software. Thus, the hardware components, particularly the instruction set of embedded processors, are specified and, consequently, the software components must be expressed in the terms of this set. For the design efficiency, the algorithms of the software components are described as programs in a high-level language and a dedicated compiler maps them into machine code. Since the hardware-software partitioning step is typically based on rough estimations, it is necessary to simulate both parts on a host computer in order to verify that all constraints in the system specification are met. If not, re-partitioning is performed and the instruction set is redefined (and the application-dedicated programs are recompiled) until a valid system implementation is found. To avoid the necessity of a separate compiler for each different instruction set, flexible retargetable compilers are necessary, which can be quickly adapted to new target processors. In addition, compilers for embedded software need to perform optimizations on the generated code. The author of this book concentrates on code generation for embedded processors and target processor modelling (which includes instruction-set specification). In particular he considers digital signal processors, very commonly used in embedded systems in areas of telecommunication and image processing. After introducing (in the chapter 1) the basic notions and presenting the considered problems, he gives in chapter 2 an introduction of the MIMOLA hardware description language, implemented in the form of the prototype compiler system RECORD. The chapter 3 presents a novel and fast technique of the analysis of processor models. Chapter 4 focusses on the tasks of code selection, register allocation and scheduling. Exploitation of potential parallelism in generated machine programs is the subject of chapter 5. A new algorithm for address generation and assignment and a novel method for code compaction (based on integer programming methods) are there presented. The capabilities of the RECORD compiler in terms of retargetability and code quality are experimentally evaluated in chapter 6. Chapter 7 concludes with a summary and hints for further research. A MIMOLA program is given in the form of an imperative language algorithm, described in a hardware-oriented superset of the PASCAL language. It is used only for describing the target processor hardware. The algorithms of the software components are formulated in a programming language DFL (Data Flow Language) designed for digital signal processors and described in the chapter 4. The code generation is the multistep process where both descriptions (of the hardware and software components) are analyzed and determine the target code.","type":"string"},"datatype":"string"},"type":"statement","id":"Q4344157$B2BC5855-3338-4557-B84D-0449CE1D3FE6","rank":"normal"}]},"sitelinks":{"mardi":{"site":"mardi","title":"Publication:4344157","badges":[],"url":"https://portal.mardi4nfdi.de/wiki/Publication:4344157"}}}}}