The following pages link to Melvin A. Breuer (Q1079543):
Displaying 31 items.
- An optimum testing algorithm for some symmetric coherent systems (Q1079544) (← links)
- Test schedules for VLSI circuits having built-in test hardware (Q1101073) (← links)
- (Q1207448) (redirect page) (← links)
- Self-diagnosis of regular arrays of processors (Q1207449) (← links)
- An unexpected result in coding the vertices of a graph (Q2527412) (← links)
- Combinatorial equivalence of (0,1) circulant matrices (Q2529626) (← links)
- Incremental Processing Applied to Munkres’ Algorithm and Its Application in Steinberg’s Placement Procedure (Q3687699) (← links)
- On Redundancy and Fault Detection in Sequential Circuits (Q3856655) (← links)
- Functional Level Primitives in Test Generation (Q3869270) (← links)
- Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis (Q3877570) (← links)
- A probabilistic model for the analysis of the routing process for circuits (Q3880783) (← links)
- Probabilistic Aspects of Boolean Switching Functions via a New Transform (Q3912727) (← links)
- A Fault-Collapsing Analysis in Sequential Logic Networks (Q3914899) (← links)
- Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect–Cause Analysis (Q3958396) (← links)
- Procedures for Eliminating Static and Dynamic Hazards in Test Generation (Q4055561) (← links)
- The Effects of Races, Delays, and Delay Faults on Test Generation (Q4055562) (← links)
- Identification of Multiple Stuck-Type Faults in Combinational Networks (Q4079515) (← links)
- (Q4159312) (← links)
- A forced directed component placement procedure for printed circuit boards (Q4198667) (← links)
- Testable MUTEX Design (Q5007399) (← links)
- Implementation of Threshold Nets by Integer Linear Programming (Q5339896) (← links)
- Techniques for the simulation of computer logic (Q5345257) (← links)
- Coding the vertexes of a graph (Q5519690) (← links)
- Adaptive computers (Q5542552) (← links)
- Generation of optimal code for expressions via factorization (Q5563773) (← links)
- Simplification of the Covering Problem with Application to Boolean Expressions (Q5594965) (← links)
- Functional Partitioning and Simulation of Digital Circuits (Q5617290) (← links)
- A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits (Q5632459) (← links)
- A Note on Three-Valued Logic Simulation (Q5636789) (← links)
- Generation of Fault Tests for Linear Logic Networks (Q5638214) (← links)
- The Borel-Tanner distribution (Q5727130) (← links)
