The following pages link to Javier D. Bruguera (Q1580034):
Displaying 18 items.
- (Q686625) (redirect page) (← links)
- Design of a pipelined radix 4 CORDIC processor (Q686627) (← links)
- Gaussian elimination with pivoting on hypercubes (Q916304) (← links)
- Parallel quadrant interlocking factorization on hypercube computers (Q919737) (← links)
- Multilevel reverse-carry addition: Single and dual adders (Q1405460) (← links)
- Very-high radix CORDIC rotation based on selection by rounding (Q1580035) (← links)
- SOFTWARE TOOLS FOR MULTIPROCESSOR SIMULATION AND PROGRAMMING (Q3352477) (← links)
- Leading-one prediction with concurrent position correction (Q3417059) (← links)
- Unified mixed radix 2-4 redundant CORDIC processor (Q4420853) (← links)
- A Digit-by-Digit Algorithm for mth Root Extraction (Q4564262) (← links)
- High-speed double-precision computation of reciprocal, division, square root, and inverse square root (Q4571227) (← links)
- Computation of √(x/d) in a very high radix combined division/square-root unit with scaling and selection by rounding (Q4571441) (← links)
- A Radix-2 Digit-by-Digit Architecture for Cube Root (Q4589567) (← links)
- (Q4786114) (← links)
- Low Latency Floating-Point Division and Square Root Unit (Q5211794) (← links)
- Fast Radix-10 Multiplication Using Redundant BCD Codes (Q5268094) (← links)
- Iterative Algorithm and Architecture for Exponential, Logarithm, Powering, and Root Extraction (Q5274497) (← links)
- Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate (Q5280492) (← links)
