Pages that link to "Item:Q1820578"
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The following pages link to Modalities for model checking: Branching time logic strikes back (Q1820578):
Displaying 18 items.
- Synthesis of large dynamic concurrent programs from dynamic specifications (Q346790) (← links)
- CTRL: extension of CTL with regular expressions and fairness operators to verify genetic regulatory networks (Q548484) (← links)
- Global and local views of state fairness (Q804304) (← links)
- A taxonomy of fairness and temporal logic problems for Petri nets (Q805257) (← links)
- Automated analysis of mutual exclusion algorithms using CCS (Q911263) (← links)
- A Rice-style theorem for parallel automata (Q1004287) (← links)
- Problems concerning fairness and temporal logic for conflict-free Petri nets (Q1121023) (← links)
- Safety, liveness and fairness in temporal logic (Q1343862) (← links)
- A methodology for designing proof rules for fair parallel programs (Q1377299) (← links)
- On temporal logic versus Datalog (Q1401358) (← links)
- Systolic tree \(\omega\)-languages: The operational and the logical view (Q1575949) (← links)
- A compositional approach to CTL\(^*\) verification (Q1770366) (← links)
- An infinite hierarchy of temporal logics over branching time (Q1854487) (← links)
- The complexity of propositional linear temporal logics in simple cases (Q1854521) (← links)
- Employing symmetry reductions in model checking (Q1886448) (← links)
- Model checking LTL with regular valuations for pushdown systems (Q1887158) (← links)
- (Q5111621) (← links)
- Dissecting \texttt{ltlsynt} (Q6151759) (← links)
