Minimizing lateness for precedence graphs with constant delays on dedicated pipelined processors (Q2883650): Difference between revisions

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Property / author: Claire Hanen / rank
 
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Property / MaRDI profile type: MaRDI publication profile / rank
 
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Property / full work available at URL
 
Property / full work available at URL: https://doi.org/10.1016/j.endm.2010.05.100 / rank
 
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Property / OpenAlex ID
 
Property / OpenAlex ID: W1983452345 / rank
 
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Property / cites work
 
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Latest revision as of 05:25, 5 July 2024

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Minimizing lateness for precedence graphs with constant delays on dedicated pipelined processors
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    Minimizing lateness for precedence graphs with constant delays on dedicated pipelined processors (English)
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    13 May 2012
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    scheduling theory
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    dedicated processors
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    unit execution times
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    precedence delays
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    maximum lateness
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    worst-case analysis
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