A method of synthesis of irredundant circuits admitting single fault detection tests of constant length (Q1741482): Difference between revisions

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+https://doi.org/10.1515/dma-2019-0005
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+Easily Testable Realizations ror Logic Functions
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+On Minimally Testable Logic Networks
@@ Property / cites work: On Minimally Testable Logic Networks / rank @@
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+Design of easily testable combinational circuits
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+Dual-Mode Logic for Function-Independent Fault Testing
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+Q3197775
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+Method of synthesis of easily testable circuits admitting single fault detection tests of constant length
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+Q3807128
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+Synthesis of easily-tested circuits in the case of single-type constant malfunctions at the element outputs
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+Circuits admitting single-fault tests of length 1 under constant faults at outputs of elements
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+Synthesis of easily testable circuits over the Zhegalkin basis in the case of constant faults of type 0 at outputs of elements
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+Lower estimate of the length of the complete test in the basis \(\{x|y \}\)
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+On the synthesis of circuits admitting complete fault detection test sets of constant length under arbitrary constant faults at the outputs of the gates
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+On the exact value of the length of the minimal single diagnostic test for a particular class of circuits
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+LOWER BOUNDS FOR LENGTHS OF COMPLETE DIAGNOSTIC TESTS FOR CIRCUITS AND INPUTS OF CIRCUITS
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+SINGLE FAULT DETECTION TESTS FOR LOGIC NETWORKS OF AND, NOT GATES
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+On reliability of circuits over an arbitrary complete finite basis under single-type constant faults at outputs of elements
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+On the circuits reliability in ``anticonjunction'' basis with constant faults at gate inputs
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