Static and dynamic processor scheduling disciplines in heterogeneous parallel architectures (Q1898192): Difference between revisions
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| Property / DOI: 10.1006/jpdc.1995.1085 / rank | |||
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| Property / author: Daniel A. Menasce / rank | |||
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| Property / author: Daniel A. Menasce / rank | |||
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| Property / MaRDI profile type: MaRDI publication profile / rank | |||
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| Property / full work available at URL: https://doi.org/10.1006/jpdc.1995.1085 / rank | |||
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| Property / OpenAlex ID: W2075666301 / rank | |||
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| Property / DOI: 10.1006/JPDC.1995.1085 / rank | |||
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Latest revision as of 12:22, 16 December 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Static and dynamic processor scheduling disciplines in heterogeneous parallel architectures |
scientific article |
Statements
Static and dynamic processor scheduling disciplines in heterogeneous parallel architectures (English)
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26 March 1996
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largest task first minimum finish time
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