Formal reasoning under cached address translation (Q2209539): Difference between revisions

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+https://doi.org/10.1007/s10817-019-09539-7
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+Physical addressing on real hardware in Isabelle/HOL
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+Concerned with the unprivileged: user programs in kernel refinement
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+A Trustworthy Monadic Formalization of the ARMv7 Instruction Set Architecture
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+Deep Specifications and Certified Abstraction Layers
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+Types, Maps and Separation Logic
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+Q4247084
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+Isabelle/HOL. A proof assistant for higher-order logic
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+A Brief Overview of HOL4
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+Reasoning about Translation Lookaside Buffers
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+Program verification in the presence of cached address translation
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+Q126318699
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