Formal reasoning under cached address translation (Q2209539): Difference between revisions

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+https://doi.org/10.1007/s10817-019-09539-7
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+W2999427823
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@@ Property / cites work @@
+Physical addressing on real hardware in Isabelle/HOL
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@@ Property / cites work @@
+Concerned with the unprivileged: user programs in kernel refinement
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@@ Property / cites work @@
+A Trustworthy Monadic Formalization of the ARMv7 Instruction Set Architecture
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+Deep Specifications and Certified Abstraction Layers
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@@ Property / cites work @@
+Types, Maps and Separation Logic
@@ Property / cites work: Types, Maps and Separation Logic / rank @@
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+Q4247084
@@ Property / cites work: Q4247084 / rank @@
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@@ Property / cites work @@
+Isabelle/HOL. A proof assistant for higher-order logic
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@@ Property / cites work @@
+A Brief Overview of HOL4
@@ Property / cites work: A Brief Overview of HOL4 / rank @@
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@@ Property / cites work @@
+Reasoning about Translation Lookaside Buffers
@@ Property / cites work: Reasoning about Translation Lookaside Buffers / rank @@
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@@ Property / cites work @@
+Program verification in the presence of cached address translation
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+Q126318699
@@ Property / Wikidata QID: Q126318699 / rank @@
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