Formal reasoning under cached address translation (Q2209539): Difference between revisions

From MaRDI portal
Set OpenAlex properties.
Created claim: Wikidata QID (P12): Q126318699, #quickstatements; #temporary_batch_1722379068559
 
(One intermediate revision by one other user not shown)
Property / cites work
 
Property / cites work: Physical addressing on real hardware in Isabelle/HOL / rank
 
Normal rank
Property / cites work
 
Property / cites work: Concerned with the unprivileged: user programs in kernel refinement / rank
 
Normal rank
Property / cites work
 
Property / cites work: A Trustworthy Monadic Formalization of the ARMv7 Instruction Set Architecture / rank
 
Normal rank
Property / cites work
 
Property / cites work: Deep Specifications and Certified Abstraction Layers / rank
 
Normal rank
Property / cites work
 
Property / cites work: Types, Maps and Separation Logic / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q4247084 / rank
 
Normal rank
Property / cites work
 
Property / cites work: Isabelle/HOL. A proof assistant for higher-order logic / rank
 
Normal rank
Property / cites work
 
Property / cites work: A Brief Overview of HOL4 / rank
 
Normal rank
Property / cites work
 
Property / cites work: Reasoning about Translation Lookaside Buffers / rank
 
Normal rank
Property / cites work
 
Property / cites work: Program verification in the presence of cached address translation / rank
 
Normal rank
Property / Wikidata QID
 
Property / Wikidata QID: Q126318699 / rank
 
Normal rank

Latest revision as of 23:39, 30 July 2024

scientific article
Language Label Description Also known as
English
Formal reasoning under cached address translation
scientific article

    Statements

    Formal reasoning under cached address translation (English)
    0 references
    0 references
    0 references
    2 November 2020
    0 references
    TLB
    0 references
    cached address translation
    0 references
    program verification
    0 references
    Formal reasoning under cached address translation
    0 references
    ARM
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references

    Identifiers

    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references