Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors. (Q1426130): Difference between revisions
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Revision as of 00:18, 29 February 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors. |
scientific article |
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Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors. (English)
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14 March 2004
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SAT-checkers
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decision diagrams
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equality with uninterpreted functions and memories
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