FPGA based high performance double-precision matrix multiplication (Q987759): Difference between revisions
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Revision as of 21:21, 30 January 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | FPGA based high performance double-precision matrix multiplication |
scientific article |
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FPGA based high performance double-precision matrix multiplication (English)
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13 August 2010
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high performance computing
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matrix multiplication
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rank-1 scheme
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FPGA implementation
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memory-bandwidth trade-off
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scalability
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