Minimizing lateness for precedence graphs with constant delays on dedicated pipelined processors (Q2883650): Difference between revisions
From MaRDI portal
Created a new Item |
Added link to MaRDI item. |
||
links / mardi / name | links / mardi / name | ||
Revision as of 20:31, 3 February 2024
scientific article
Language | Label | Description | Also known as |
---|---|---|---|
English | Minimizing lateness for precedence graphs with constant delays on dedicated pipelined processors |
scientific article |
Statements
Minimizing lateness for precedence graphs with constant delays on dedicated pipelined processors (English)
0 references
13 May 2012
0 references
scheduling theory
0 references
dedicated processors
0 references
unit execution times
0 references
precedence delays
0 references
maximum lateness
0 references
worst-case analysis
0 references