Processor array synthesis from shift-variant deep nested Do loops (Q1402301): Difference between revisions
From MaRDI portal
Added link to MaRDI item. |
Changed an Item |
||
Property / describes a project that uses | |||
Property / describes a project that uses: DG2VHDL / rank | |||
Normal rank |
Revision as of 07:42, 29 February 2024
scientific article
Language | Label | Description | Also known as |
---|---|---|---|
English | Processor array synthesis from shift-variant deep nested Do loops |
scientific article |
Statements
Processor array synthesis from shift-variant deep nested Do loops (English)
0 references
20 August 2003
0 references
reconfigurable computing
0 references
FPGA
0 references
nested loop
0 references
systolic mapping
0 references
motion estimation
0 references