High-performance bidiagonal reduction using tile algorithms on homogeneous multicore architectures (Q3189674): Difference between revisions

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Revision as of 20:31, 19 March 2024

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High-performance bidiagonal reduction using tile algorithms on homogeneous multicore architectures
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    High-performance bidiagonal reduction using tile algorithms on homogeneous multicore architectures (English)
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    12 September 2014
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    bidiagional reduction
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    bulge chasing
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    data translation layer
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    dynamic scheduling
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    high performance kernels
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    tile algorithms
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    two-stage approach
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