Floorplanning by graph dualization: \(L\)-shaped modules (Q1310461): Difference between revisions
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| Property / cites work: A linear time algorithm to check for the existence of a rectangular dual of a planar triangulated graph / rank | |||
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| Property / cites work: A linear algorithm to find a rectangular dual of a planar triangulated graph / rank | |||
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| Property / cites work: On the number of cycles of lengthk in a maximal planar graph / rank | |||
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| Property / cites work: Finding a Minimum Circuit in a Graph / rank | |||
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| Property / cites work: Rectangular duals of planar graphs / rank | |||
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| Property / cites work: Rectangular dualization and rectangular dissections / rank | |||
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| Property / cites work: Floorplan design of VLSI circuits / rank | |||
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Revision as of 11:11, 22 May 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Floorplanning by graph dualization: \(L\)-shaped modules |
scientific article |
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Floorplanning by graph dualization: \(L\)-shaped modules (English)
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6 January 1994
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VLSI
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floorplanning
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adjacency graph
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graph dualization
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\(L\)-shaped modules
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\(L\)-shaped dual
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