New lower bound techniques for VLSI (Q3950484): Difference between revisions
From MaRDI portal
Set profile property. |
ReferenceBot (talk | contribs) Changed an Item |
||
| Property / cites work | |||
| Property / cites work: A model of computation for VLSI with related complexity results / rank | |||
Normal rank | |||
| Property / cites work | |||
| Property / cites work: The crossing number of K5,n / rank | |||
Normal rank | |||
| Property / cites work | |||
| Property / cites work: Applications of a Planar Separator Theorem / rank | |||
Normal rank | |||
| Property / cites work | |||
| Property / cites work: Bounds to Complexities of Networks for Sorting and for Switching / rank | |||
Normal rank | |||
| Property / cites work | |||
| Property / cites work: Q3667941 / rank | |||
Normal rank | |||
| Property / cites work | |||
| Property / cites work: Area-time optimal VLSI networks for multiplying matrices / rank | |||
Normal rank | |||
| Property / cites work | |||
| Property / cites work: The VLSI Complexity of Sorting / rank | |||
Normal rank | |||
| Property / cites work | |||
| Property / cites work: Universality considerations in VLSI circuits / rank | |||
Normal rank | |||
Revision as of 15:15, 13 June 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | New lower bound techniques for VLSI |
scientific article |
Statements
New lower bound techniques for VLSI (English)
0 references
1984
0 references
crossing number
0 references
wire area
0 references
layout area
0 references
maximum edge length
0 references
N-node planar graph
0 references
area-efficient chip layouts
0 references
bisection width
0 references
graph embedding
0 references
mesh of trees
0 references
parallel computation
0 references
separator
0 references
Thompson grid model
0 references
tree of meshes
0 references
very large scale integration
0 references
wire length
0 references
