Simulating circuit-level simplifications on CNF (Q352967): Difference between revisions

From MaRDI portal
Set OpenAlex properties.
ReferenceBot (talk | contribs)
Changed an Item
Property / cites work
 
Property / cites work: Theory and Applications of Satisfiability Testing / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q4817533 / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q5503674 / rank
 
Normal rank
Property / cites work
 
Property / cites work: Blocked Clause Elimination for QBF / rank
 
Normal rank
Property / cites work
 
Property / cites work: An optimality result for clause form translation / rank
 
Normal rank
Property / cites work
 
Property / cites work: A Computing Procedure for Quantification Theory / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q5724242 / rank
 
Normal rank
Property / cites work
 
Property / cites work: Towards feasible solutions of the tautology problem / rank
 
Normal rank
Property / cites work
 
Property / cites work: Theory and Applications of Satisfiability Testing / rank
 
Normal rank
Property / cites work
 
Property / cites work: Applying Logic Synthesis for Speeding Up SAT / rank
 
Normal rank
Property / cites work
 
Property / cites work: A Decision Procedure for Bit-Vectors and Arrays / rank
 
Normal rank
Property / cites work
 
Property / cites work: Theory and Applications of Satisfiability Testing / rank
 
Normal rank
Property / cites work
 
Property / cites work: Theory and Applications of Satisfiability Testing / rank
 
Normal rank
Property / cites work
 
Property / cites work: Exact DFA Identification Using SAT Solvers / rank
 
Normal rank
Property / cites work
 
Property / cites work: Extended clause learning / rank
 
Normal rank
Property / cites work
 
Property / cites work: Theory and Applications of Satisfiability Testing / rank
 
Normal rank
Property / cites work
 
Property / cites work: Reconstructing Solutions after Blocked Clause Elimination / rank
 
Normal rank
Property / cites work
 
Property / cites work: Blocked Clause Elimination / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q2741510 / rank
 
Normal rank
Property / cites work
 
Property / cites work: New methods for 3-SAT decision and worst-case analysis / rank
 
Normal rank
Property / cites work
 
Property / cites work: On a generalization of extended resolution / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q2741514 / rank
 
Normal rank
Property / cites work
 
Property / cites work: Combining Adaptive Noise and Look-Ahead in Local Search for SAT / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q4475702 / rank
 
Normal rank
Property / cites work
 
Property / cites work: A structure-preserving clause form translation / rank
 
Normal rank
Property / cites work
 
Property / cites work: Solving Satisfiability with Less Searching / rank
 
Normal rank
Property / cites work
 
Property / cites work: Theory and Applications of Satisfiability Testing / rank
 
Normal rank
Property / cites work
 
Property / cites work: Theory and Applications of Satisfiability Testing / rank
 
Normal rank
Property / cites work
 
Property / cites work: Toward leaner binary-clause reasoning in a satisfiability solver / rank
 
Normal rank

Revision as of 14:25, 6 July 2024

scientific article
Language Label Description Also known as
English
Simulating circuit-level simplifications on CNF
scientific article

    Statements

    Simulating circuit-level simplifications on CNF (English)
    0 references
    0 references
    0 references
    0 references
    5 July 2013
    0 references
    Boolean satisfiability
    0 references
    preprocessing
    0 references
    problem structure
    0 references
    blocked clauses
    0 references
    variable elimination
    0 references
    Boolean circuits
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references
    0 references

    Identifiers