Automatic verification of reduction techniques in higher order logic
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Publication:469363
DOI10.1007/s00165-012-0223-xzbMath1298.68162OpenAlexW2007666139MaRDI QIDQ469363
Sa'ed Abed, Ghiath Al Sammane, Otmane Ait Mohamed
Publication date: 10 November 2014
Published in: Formal Aspects of Computing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s00165-012-0223-x
Logic in artificial intelligence (68T27) Specification and verification (program logics, model checking, etc.) (68Q60)
Uses Software
Cites Work
- Equational abstractions
- Symbolic model checking for real-time systems
- Introduction to the OBDD algorithm for the ATP community
- On the non-termination of MDG-based abstract state enumeration
- Edinburgh LCF. A mechanized logic of computation
- Programming a Symbolic Model Checker in a Fully Expansive Theorem Prover
- Graph-Based Algorithms for Boolean Function Manipulation
- Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs)
- Equational Abstractions for Reducing the State Space of Rewrite Theories
- A machine program for theorem-proving
- Deciding Bit-Vector Arithmetic with Abstraction
- Computer Aided Verification
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