Performance evaluation of SNAIL: a multiprocessor based on the simple serial synchronized multistage interconnection network architecture

DOI10.1016/S0167-8191(99)00038-1zbMath0930.68021MaRDI QIDQ1960613

Toshihiro Hanawa, Takuji Komeda, Junji Yamamoto, Takayuki Kamei, Takashi Fujiwara

Publication date: 12 January 2000

Published in: Parallel Computing (Search for Journal in Brave)

zbMATH Keywords

multiprocessorsVLSI implementationmultistage interconnection networksempirical evaluationsmessage combining

Mathematics Subject Classification ID

Computer system organization (68M99)

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