Reducing Clocks in Timed Automata while Preserving Bisimulation

DOI10.1007/978-3-662-44584-6_36zbMath1417.68102arXiv1404.6613OpenAlexW325265439MaRDI QIDQ3190141

Chinmay Narayan, Shibashis Guha, S. Arun-Kumar

Publication date: 15 September 2014

Published in: CONCUR 2014 – Concurrency Theory (Search for Journal in Brave)

Full work available at URL: https://arxiv.org/abs/1404.6613

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

Related Items (3)

An automated system repair framework with signal temporal logic ⋮ Untangling the graphs of timed automata to decrease the number of clocks ⋮ An efficient customized clock allocation algorithm for a class of timed automata

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