On polynomial-time testable combinational circuits

DOI10.1109/12.324562zbMath1061.68512OpenAlexW2000280971MaRDI QIDQ4419803

Shunichi Toida, Nageswara S. V. Rao

Publication date: 1994

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.324562

zbMATH Keywords

NP-completenesstest generation

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Reliability, testing and fault tolerance of networks and computer systems (68M15)

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