Configurable Architectures for Multi-Mode Floating Point Adders

DOI10.1109/TCSI.2015.2452351zbMath1468.68023DBLPjournals/tcas/JaiswalVSBPC15OpenAlexW1849725481WikidataQ59789561 ScholiaQ59789561MaRDI QIDQ5007947

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Publication date: 26 August 2021

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2015.2452351

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Numerical algorithms for computer arithmetic, etc. (65Y04)

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