Correct Hardware Design and Verification Methods

DOI10.1007/11560548zbMath1159.68316OpenAlexW2483257485MaRDI QIDQ5493224

Gianfranco Ciardo, Andy Jinqing Yu

Publication date: 20 October 2006

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/11560548

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical problems of computer architecture (68M07)

Related Items (7)

Symbolic synthesis of masking fault-tolerant distributed programs ⋮ Improving Saturation Efficiency with Implicit Relations ⋮ Saturation Enhanced with Conditional Locality: Application to Petri Nets ⋮ Symbolic State-Space Generation of Asynchronous Systems Using Extensible Decision Diagrams ⋮ Symbolic Reachability Analysis of Integer Timed Petri Nets ⋮ Symbolic CTL Model Checking of Asynchronous Systems Using Constrained Saturation ⋮ Symbolic Reachability for Process Algebras with Recursive Data Types

Uses Software

• SPIN
• SMART_

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