Pages that link to "Item:Q3401881"
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The following pages link to MINIMIZATION AND OPTIMIZATION OF REVERSIBLE BCD-FULL ADDER/SUBTRACTOR USING GENETIC ALGORITHM AND DON'T CARE CONCEPT (Q3401881):
Displaying 6 items.
- Optimization approaches for designing quantum reversible arithmetic logic unit (Q293885) (← links)
- A novel fault-tolerant quantum divider and its simulation (Q2107957) (← links)
- Novel qutrit circuit design for multiplexer, de-multiplexer, and decoder (Q2111000) (← links)
- T-count optimized Wallace tree integer multiplier for quantum computing (Q2239664) (← links)
- On design of parity preserving reversible adder circuits (Q2400197) (← links)
- NOVEL REVERSIBLE FAULT TOLERANT ERROR CODING AND DETECTION CIRCUITS (Q3015432) (← links)
