The following pages link to Sudhakar Yalamanchili (Q1745945):
Displaying 15 items.
- (Q313342) (redirect page) (← links)
- Performance regulation of event-driven dynamical systems using infinitesimal perturbation analysis (Q313343) (← links)
- Instruction-throughput regulation in computer processors with data-center applications (Q1745946) (← links)
- MMR: a multimedia router architecture to support hybrid workloads (Q2369679) (← links)
- (Q2777272) (← links)
- Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware (Q3389801) (← links)
- (Q4417466) (← links)
- (Q4417533) (← links)
- Augmented binary hypercube: a new architecture for processor management (Q4420873) (← links)
- Distributed, deadlock-free routing in faulty, pipelined, direct interconnection networks (Q4420980) (← links)
- A performance model of pipelined k-ary n-cubes (Q4421213) (← links)
- Parallelism in sequential multiprocessor simulation models (Q4875974) (← links)
- Advances in Computer Science - ASIAN 2004. Higher-Level Decision Making (Q5463951) (← links)
- (Q5688927) (← links)
- Temperature Regulation in Multicore Processors Using Adjustable-Gain Integral Controllers (Q6263850) (← links)