The following pages link to Daniel L. Ostapko (Q3050333):
Displayed 8 items.
- Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's) (Q3050334) (← links)
- A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks (Q3914897) (← links)
- Codes for Self-clocking, AC-coupled Transmission: Aspects of Synthesis and Analysis (Q4065421) (← links)
- MINI: A Heuristic Approach for Logic Minimization (Q4777256) (← links)
- Generating Test Examples for Heuristic Boolean Minimization (Q4777257) (← links)
- Realization of a Class of Switching Functions by Threshold-Logic Networks (Q5554372) (← links)
- Realization of an Arbitrary Switching Function with a Two-Level Network of Threshold and Parity Elements (Q5578538) (← links)
- On Complementation of Boolean Functions (Q5655293) (← links)