A New Representation for Faults in Combinational Digital Circuits

DOI10.1109/TC.1972.5009041MaRDI QIDQ5183407zbMATH OpenFDO

Authors Donald R. Schertz, Gernot Metze

Publication date 1972

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.1972.5009041

Mathematics Subject Classification ID

Cited in

(2)

• An algorithm to generate complete test sets for stuck-at faults in combinational logic circuits
• Multistep fault-collapsing method for spectral signature detecting in combinational networks

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