A configurable architecture for the wavelet packet transform

DOI10.1023/A:1020221003822MaRDI QIDQ1851104zbMATH OpenOpenAlexFDO

Authors Yanyan Li

Publication date 15 December 2002

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/a:1020221003822

zbMATH Keywords

time-frequency tilingwavelet packetsword-parallelword-serial

Mathematics Subject Classification ID

Numerical methods for wavelets (65T60) Mathematical problems of computer architecture (68M07) Image processing (compression, reconstruction, etc.) in information and communication theory (94A08) Signal theory (characterization, reconstruction, filtering, etc.) (94A12)

Recommendations

• scientific article; zbMATH DE number 1442018
• Architecture for wavelet packet transform based on lifting steps
• VLSI architectures for the discrete wavelet transform
• VLSI architectures of the 1-D and 2-D discrete wavelet transforms for JPEG 2000
• Discrete wavelet transform: Architectures, design and performance issues

Cited in

(5)

• Architecture for wavelet packet transform based on lifting steps
• Optical wavelet signals processing and multiplexing
• scientific article; zbMATH DE number 1728335 (Why is no real title available?)
• Low complexity reconfigurable architecture for the 5/3 and 9/7 discrete wavelet transform
• scientific article; zbMATH DE number 1941073 (Why is no real title available?)

This page was built for publication: A configurable architecture for the wavelet packet transform

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1851104)