A faster one-dimensional topological compaction algorithm with jog insertion

DOI10.1007/S004530010044MaRDI QIDQ1586137zbMATH OpenOpenAlexFDO

Authors R. Smith

Publication date 21 June 2001

Published in Algorithmica (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s004530010044

zbMATH Keywords

layout compactionVLSI design

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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