A generalized fault simulator for combinational logic circuits

DOI10.1016/0045-7906(89)90016-5MaRDI QIDQ805218zbMATH OpenOpenAlexFDO

Authors Rajesh Raina, T. N. Rajashekhara

Publication date 1989

Published in Computers and Electrical Engineering (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0045-7906(89)90016-5

zbMATH Keywords

automatic test pattern generationcombinational logic circuitsfault simulator

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Fault detection; testing in circuits and networks (94C12)

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Cited in

(3)

• Basic algorithms and peculiarities of program implementation of hierarchical compilative simulator
• Generalized ternary simulation of sequential circuits
• On fault simulation for synchronous sequential circuits

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