A vectorized systolic array for parallel weight extraction of block RLS

DOI10.1002/ACS.4480080504MaRDI QIDQ4312781zbMATH OpenOpenAlexFDO

Authors Hideaki Sakai

Publication date 8 November 1994

Published in International Journal of Adaptive Control and Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1002/acs.4480080504

zbMATH Keywords

block recursive least squaresfactorizationHouseholder transformationsparallel computationQR decompositionsignal processingsystolic arrayupdates

Mathematics Subject Classification ID

Numerical solutions to overdetermined systems, pseudoinverses (65F20) Parallel numerical computation (65Y05) Adaptive control/observation systems (93C40)

Recommendations

• A systolic array architecture for QR decomposition of block structured sparse systems
• Recursive least-squares using a hybrid Householder algorithm on massively parallel SIMD systems.
• Recursive least squares with stabilized inverse factorization
• Block RLS using row Householder reflections
• New approach to parallel systolic algorithm implementations -- RLSL example

Cited in

(1)

• CP-based SBHT-RLS algorithms for tracking channel estimates in multicarrier modulation systems

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