An 0(n) Parallel Multiplier with Bit-Sequential Input and Output

DOI10.1109/TC.1979.1675239MaRDI QIDQ3856659zbMATH OpenOpenAlexFDO

Authors I-Ngo Chen, Robert Willoner

Publication date 1979

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1979.1675239

zbMATH Keywords

computer arithmeticon-line algorithmsparallel multiplierpipeliningreal-time algorithms

Mathematics Subject Classification ID

Cited in

(1)

• High-radix and bit recoding techniques for modular exponentiation

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