An improved maximally redundant signed digit adder

DOI10.1016/J.COMPELECENG.2009.12.002MaRDI QIDQ974157zbMATH OpenOpenAlexFDO

Authors Ghassem Jaberipur, Saeid Gorgin

Publication date 27 May 2010

Published in Computers and Electrical Engineering (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.compeleceng.2009.12.002

zbMATH Keywords

computer arithmeticinverted encoding of negabitslogical techniques and designmaximally redundant signed-digit number systemsigned digit adderweighted bit-set encoding

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computer system organization (68M99)

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