An optimal emulator and VLSI layout for complete binary trees

DOI10.1007/S002360050093MaRDI QIDQ1920223zbMATH OpenOpenAlexFDO

Authors Nancy Eleser, Kemal Efe

Publication date 25 September 1996

Published in Acta Informatica (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s002360050093

zbMATH Keywords

binary treesgraph embeddingparallel architecturesVLSI layout

Mathematics Subject Classification ID

Trees (05C05) Graph theory (including graph drawing) in computer science (68R10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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