Analysis and optimization of a novel CMOS multiplier

DOI10.1002/CTA.146MaRDI QIDQ2764553zbMATH OpenOpenAlexFDO

Authors G. Giustolisi, G. Palmisano, G. Palumbo

Publication date 19 September 2002

Published in International Journal of Circuit Theory and Applications (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1002/cta.146

zbMATH Keywords

CMOS voltage multipliernonlinear CMOS analog circuits

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Applications of design theory to circuits and networks (94C30)

Cites work

• Simple CMOS analog square-rooting and squaring circuits

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