Approximation scheme for restricted discrete gate sizing targeting delay minimization

DOI10.1007/S10878-009-9267-0MaRDI QIDQ491218zbMATH OpenOpenAlexFDO

Authors Chen Liao, Shiyan Hu

Publication date 24 August 2015

Published in Journal of Combinatorial Optimization (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s10878-009-9267-0

zbMATH Keywords

combinatorial optimizationVLSI designfully polynomial time approximation schemedelay optimizationdiscrete gate sizing

Mathematics Subject Classification ID

Combinatorial optimization (90C27) Applications of graph theory to circuits and networks (94C15)

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Cites work

• An improved FPTAS for Restricted Shortest Path.
• Approximation Schemes for the Restricted Shortest Path Problem
• Chebyshev's approximation algorithms and applications

Cited in

(2)

• An integrative approach with sequential game to real-time gate assignment under CDM mechanism
• A convex programming solution for gate-sizing with pipelining constraints

Describes a project that uses

Uses Software

• TILOS

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