Area—Time Optimal VLSI Circuits for Convolution

DOI10.1109/TC.1983.1676300MaRDI QIDQ3659695zbMATH OpenFDO

Authors Gerard M. Baudet, F. P. Preparata, Jean E. Vuillemin

Publication date 1983

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.1983.1676300

zbMATH Keywords

area-time optimalityconvolutionVLSI design

Mathematics Subject Classification ID

Communication theory (94A05) Applications of design theory to circuits and networks (94C30)

Cited in

(2)

• Area-time tradeoffs for bilinear forms computations in VLSI
• A survey of some recent bit-parallel \(\mathrm{GF}(2^n)\) multipliers

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