Area complexity of merging
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The paper under review deals with the VLSI area complexity for merging two sorted arrays of k-bit integers. First, a lower bound is established for this problem: \(\theta(m(\log n-\log m+1))\) if \(k\geq \log n\), \(A=\{\theta(\min \{2^ k,m\}(| k-\log m| +1))\) for \(k\leq \log n\), where m and n are the sizes of the arrays with \(m\leq n\). Then, two optimal circuits corresponding to the two cases are described.
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Cites work
- A minimum-area circuit for -selection
- Area-time lower-bound techniques with applications to sorting
- scientific article; zbMATH DE number 3858396 (Why is no real title available?)
- scientific article; zbMATH DE number 3911723 (Why is no real title available?)
- scientific article; zbMATH DE number 3940717 (Why is no real title available?)
- scientific article; zbMATH DE number 4026821 (Why is no real title available?)
- scientific article; zbMATH DE number 3894473 (Why is no real title available?)
- Minimum Storage Sorting Networks
- The Area-Time Complexity of Binary Multiplication
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