Arithmetic unit design for neural accelerators: cost performance issues

DOI10.1109/12.467702MaRDI QIDQ4421178zbMATH OpenOpenAlexFDO

Authors K. Sammut, Stephanie R. Jones

Publication date 1995

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.467702

zbMATH Keywords

instruction set measurementslinear array acceleratorsneural networks

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Learning and adaptive systems in artificial intelligence (68T05)

Recommendations

• Algorithm design for tensor units
• Convolution accelerator designs using fast algorithms
• Input multiplexing in artificial neurons employing stochastic arithmetic
• Computer arithmetic and hardware: ``off the shelf microprocessors versus ``custom hardware
• GPU implementation of neural networks

Cited in

(2)

• Rethinking arithmetic for deep neural networks
• Algorithm design for tensor units

This page was built for publication: Arithmetic unit design for neural accelerators: cost performance issues

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4421178)