Clock Synchronization Errors in Circuits: Models, Stability and Fault Detection

DOI10.1109/TCSI.2006.882823MaRDI QIDQ4590580zbMATH OpenOpenAlexFDO

Authors Cédric Lorand, Peter H. Bauer

Publication date 20 November 2017

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tcsi.2006.882823

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Cited in

(4)

• Modeling of jitter in bang-bang clock and data recovery circuits
• On the stability and control of discrete linear systems with clock synchronisation errors
• Determination of clock synchronization errors in distributed networks
• New Challenges in Dynamical Systems: The Networked Case

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