Correct Hardware Design and Verification Methods

DOI10.1007/B93958MaRDI QIDQ5897075zbMATH OpenOpenAlexFDO

Authors Panagiotis Manolios

Publication date 5 February 2010

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/b93958

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Recommendations

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Cited in

(8)

• Expressive completeness failure in branching time structures
• Twenty years of rewriting logic
• Specification and verification of concurrent programs through refinements
• Universal extensions to simulate specifications
• Simulation refinement for concurrency verification
• The existence of refinement mappings
• Algebraic simulations
• A framework for verifying bit-level pipelined machines based on automated deduction and decision procedures

Describes a project that uses

Uses Software

• SATO
• Chaff

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