Dense CMOS implementation of a binary-programmable cellular neural network
From MaRDI portal
Recommendations
- Compact CMOS implementation of a low-power, current-mode programmable cellular neural network
- A configurable digital cellular neural network with template decomposition
- Image-processing algorithms realized by discrete-time cellular neural networks and their circuit implementations
- scientific article; zbMATH DE number 1974053
- Current-mode techniques for the implementation of continuous- and discrete-time cellular neural networks
Cited in
(10)- Compact CMOS implementation of a low-power, current-mode programmable cellular neural network
- A binary-based on-chip CNN solution for pixel-level snakes
- Digital implementation of cellular sensor-computers
- Stochastic bitstream-based CNN and its implementation on FPGA
- Current-mode techniques for the implementation of continuous- and discrete-time cellular neural networks
- A behavioural modelling technique for visual microprocessor mixed‐signal VLSI chips
- ORIENTED SPATIAL PATTERN FORMATION IN A FOUR LAYER CMOS CELLULAR NEURAL NETWORK
- A configurable digital cellular neural network with template decomposition
- Image-processing algorithms realized by discrete-time cellular neural networks and their circuit implementations
- A CNN-specific integrated processor
This page was built for publication: Dense CMOS implementation of a binary-programmable cellular neural network
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3425476)