Developing a hardware evaluation method for SHA-3 candidates

DOI10.1007/978-3-642-15031-9_17MaRDI QIDQ3583461zbMATH OpenOpenAlexFDO

Authors Luca Henzen, Pietro Gendotti, Patrice Guillet, Enrico Pargaetzi, Martin Zoller, Frank K. Gürkaynak

Publication date 17 August 2010

Published in Cryptographic Hardware and Embedded Systems, CHES 2010 (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-642-15031-9_17

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Cryptography (94A60)

Recommendations

• Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs
• Performance analysis of the SHA-3 candidates on exotic multi-core architectures
• Lightweight implementations of SHA-3 candidates on FPGAs
• Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs
• Side-channel analysis of six SHA-3 candidates

Cited in

(6)

• Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID
• The NIST SHA-3 Competition: A Perspective on the Final Year
• Lightweight implementations of SHA-3 candidates on FPGAs
• Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs
• Performance analysis of the SHA-3 candidates on exotic multi-core architectures
• XBX: external benchmarking extension for the SUPERCOP crypto benchmarking framework

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