EVC
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Cited in
(9)- Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs)
- tts
- Velev SAT Benchmarks
- Automatic abstraction of equations in a logic of equality
- Building small equality graphs for deciding equality logic with uninterpreted functions
- Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors.
- Producing and verifying extremely large propositional refutations
- Theorem Proving in Higher Order Logics
- scientific article; zbMATH DE number 1701763 (Why is no real title available?)
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