EVC

swMATH13374MaRDI QIDQ25288FDOQ25288

Author name not available (Why is that?)

Official website: http://link.springer.com/chapter/10.1007/3-540-44585-4_20

Cited In (9)

• Producing and verifying extremely large propositional refutations
• Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors.
• Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs)
• Building small equality graphs for deciding equality logic with uninterpreted functions
• tts
• Velev SAT Benchmarks
• Theorem Proving in Higher Order Logics
• Automatic abstraction of equations in a logic of equality
• Title not available (Why is that?)

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