Expressiveness of verifiable hierarchical clock systems

DOI10.1080/03081070701794876MaRDI QIDQ3005130zbMATH OpenOpenAlexFDO

Authors Moon Ho Hwang, Bernard P. Zeigler

Publication date 7 June 2011

Published in International Journal of General Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1080/03081070701794876

zbMATH Keywords

DEVSgeneral dynamical systemhierarchical I/O clock systemtimed automataverification

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85) Discrete event control/observation systems (93C65)

Recommendations

• The Theory of Timed I/O Automata
• The expressive power of clocks
• scientific article; zbMATH DE number 1400049
• Discrete events and general systems theory
• The theory of timed I/O automata

Cites work

• A theory of timed automata
• An environment for DEVS-based multiformalism simulation in common lisp/CLOS
• Analysis of timed systems using time-abstracting bisimulations
• Discrete Event Simulation of Hybrid Systems
• scientific article; zbMATH DE number 3904008 (Why is no real title available?)
• scientific article; zbMATH DE number 46228 (Why is no real title available?)
• scientific article; zbMATH DE number 3548491 (Why is no real title available?)
• scientific article; zbMATH DE number 1228291 (Why is no real title available?)
• Model-checking in dense real-time
• SYSTEM THEORETIC FORMALISMS FOR COMBINED DISCRETE-CONTINUOUS SYSTEM SIMULATION

Cited in

(2)

• REALIZATION THEORY OF DISCRETE-EVENT SYSTEMS AND ITS APPLICATION TO THE UNIQUENESS AND UNIVERSALITY OF DEVS FORMALISM
• On the verification of timed discrete-event models

Describes a project that uses

Uses Software

• CLOS

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