FPGA Designs with Optimized Logarithmic Arithmetic

DOI10.1109/TC.2010.51MaRDI QIDQ5280741zbMATH OpenFDO

Authors Haohuan Fu, Oskar Mencer, Wayne Luk

Publication date 27 July 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.2010.51

Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04) Cryptography (94A60)

Cited in

(4)

• A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor
• 5 Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks of FPGAs
• Guide to FPGA implementation of arithmetic functions
• FPGA REALIZATION OF COMPLEX LOGISTIC MAP FRACTAL BEHAVIOR

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