Fault Equivalence in Combinational Logic Networks

DOI10.1109/T-C.1971.223129MaRDI QIDQ5639633zbMATH OpenOpenAlexFDO

Authors Edward J. McCluskey, Frederick W. Clegg

Publication date 1971

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/t-c.1971.223129

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Cited in

(4)

• An algorithm to generate complete test sets for stuck-at faults in combinational logic circuits
• On the construction of hierarchic models
• Transition submatrices in regular homing experiments and identification of sequential machines of known class using direct-sum transition matrices
• Toward a definition of fault analysis for Petri nets models

This page was built for publication: Fault Equivalence in Combinational Logic Networks

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5639633)