Formally verifying fault tolerant system designs
From MaRDI portal
Recommendations
Cited in
(17)- Automating the addition of fault tolerance with discrete controller synthesis
- Design and verification of fault tolerant systems with CSP
- Machine checked proofs of the design of a fault-tolerant circuit
- A compositional framework for fault tolerance by specification transformation
- Simulation relations for fault-tolerance
- An object based algebra for specifying a fault tolerant software architecture
- scientific article; zbMATH DE number 1629970 (Why is no real title available?)
- Logical specification and analysis of fault tolerant systems through partial model checking
- dCTL: a branching time temporal logic for fault-tolerant system verification
- scientific article; zbMATH DE number 3890717 (Why is no real title available?)
- Towards Formal Fault Tree Analysis Using Theorem Proving
- Design and Verification of Fault-Tolerant Components
- scientific article; zbMATH DE number 1107558 (Why is no real title available?)
- scientific article; zbMATH DE number 1543325 (Why is no real title available?)
- scientific article; zbMATH DE number 1444728 (Why is no real title available?)
- Experiments on a fault tolerant distributed system
- Model-based construction and verification of critical systems using composition and partial refinement
This page was built for publication: Formally verifying fault tolerant system designs
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2730080)