Heuristic method to check the realisability of a graph into a rectangular plan

DOI10.1016/S0965-9978(99)00023-XMaRDI QIDQ1575024zbMATH OpenFDO

Authors N. Delaunay, Alfonso Recuero, O. Río, M. Alvarez

Publication date 14 August 2000

Published in Advances in Engineering Software (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/S0965-9978(99)00023-X

zbMATH Keywords

architectural designcompacting of electronic circuits

Mathematics Subject Classification ID

Computer science aspects of computer-aided design (68U07)

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